M14D2561616A Datasheet, PDF (13/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
Parameter
Minimum time clocks remains
ON after CKE asynchronously
drops low
Output impedance test driver
delay
MRS command to ODT update
delay
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down
mode)
Symbol
-2.5
Min.
Max.
t_DELAY t_IS + t_CK (avg)+t_IH
-
-3
Min.
Max.
t_IS + t_CK (avg)+t_IH
-
t_OIT
0
12
0
12
t_MOD
0
12
0
12
t_AOND
t_AON
t_AONPD
2
2
2
2
t_AC(min.) t_AC(max.) + 700
t_AC(min.)
2 x t_CK
t_AC(min.) + 2000 +t_AC(max.) +
1000
t_AC(min.) + 2000
t_AC(max.) +
700
2 x t_CK
+t_AC(max.) +
1000
ODT turn-off delay
t_AOFD
2.5
2.5
2.5
2.5
ODT turn-off
ODT turn-off (Power-Down
mode)
ODT to Power-Down entry
latency
t_AOF
t_AOFPD
t_AC(min.) t_AC(max.) + 600
2.5 x t_CK
t_AC(min.) + 2000 +t_AC(max.) +
1000
t_AC(min.)
t_AC(min.) + 2000
t_AC(max.) +
600
2.5 x t_CK
+t_AC(max.) +
1000
t_ANPD
3
3
3
3
ODT Power-Down exit latency
t_AXPD
8
8
8
8
Note:
1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
Unit Note
ns
ns
ns
t_CK
ps 14,16
ps
t_CK
15,17
,18
ps
ps
t_CK
t_CK
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
6. t_HP is the minimum of the absolute half period of the actual input clock. t_HP is an input parameter but not an input
specification parameter. It is used in conjunction with t_QHS to derive the DRAM output timing t_QH. The value to be used for t_QH
calculation is determined by the following equation;
t_HP = Min ( t_CH (abs), t_CL (abs) ), where:
t_CH (abs) is the minimum of the actual instantaneous clock HIGH time;
t_CL (abs) is the minimum of the actual instantaneous clock LOW time;
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
13/59