M12L64322A_07 Datasheet, PDF (6/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHZ)
Parameter
Symbol
Min
Input capacitance (A0 ~ A10, BA0 ~ BA1)
CIN1
2
Input capacitance
CIN2
2
(CLK, CKE, CS , RAS , CAS , WE & DQM)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
M12L64322A
Max
Unit
4
pF
4
pF
5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Symbol
Test Condition
CAS
Latency
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
Burst Length = 1
tRC ≥ tRC(min)
IOL = 0 mA
CKE ≤ VIL(max), tcc = 15ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
CKE ≤ VIL(max), tcc = 15ns
CKE & CLK ≤ VIL(max), tcc = ∞
Version
Unit
-5 -6 -7
180 _{160 140} mA
2
mA
2
30
mA
10
10
mA
10
Note
1,2
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
40
mA
Input signals are changed one time during 30ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
10
mA
IOL = 0 mA
ICC4
Page Burst
2 Banks activated
3
280 250 220
mA 1,2
2
220 200 180
ICC5
tRC ≥ tRC(min)
330 310 285 mA
ICC6
CKE ≤ 0.2V
2
mA
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
6/47