M12L64322A_07 Datasheet, PDF (33/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18
19
CKE
CS
RAS
CAS
tRCD
t *Note1
RC
HIGH
*Note2
ADDR
Ra
Ca
Rb
Cb
BA1
BA0
A10/AP
Ra
CL=2
DQ
CL=3
WE
DQM
Rb
`
tOH
Qa0
tSAC
Qa1 Qa2
tOH
Qa0 Qa1
tSAC
Qa3
tSHZ
*Note3
Qa2
Qa3
tSHZ *Note3
Db0 Db1
Db2 Db3
tRDL
Db0 Db1 Db2 Db3
tRDL
Row Active
( A- Ban k)
Read
( A- Ban k)
Precharge
( A- Ban k)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
33/47