M12L64322A_07 Datasheet, PDF (11/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA0~BA1
RFU
A10/AP
RFU
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
W.B.L
TM
CAS Latency
BT
Burst Length
Test Mode
A8 A7
Type
A6
0
0 Mode Register Set 0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
0
Write Burst Length
1
A9
Length
1
0
Burst
1
1
Single Bit
1
CAS Latency
Burst Type
Burst Length
A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1
0
0 Reserved 0 Sequential 0
0
0
1
1
0
1 Reserved 1 Interleave 0
0
1
2
2
1
0
2
0
1
0
4
4
1
1
3
0
1
1
8
8
0
0 Reserved
1
0
0 Reserved Reserved
0
1 Reserved
1
0
1 Reserved Reserved
1
0 Reserved
1
1
0 Reserved Reserved
1
1 Reserved
1
1
1 Full Page Reserved
Full Page Length : 256
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
11/47