M12L64322A_07 Datasheet, PDF (5/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
PIN
DQM0~3
DQ0 ~ DQ31
VDD / VSS
VDDQ / VSSQ
N.C
NAME
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 °C )
Parameter
Symbol
Min
Supply voltage
VDD, VDDQ
3.0
Input logic high voltage
VIH
2.0
Input logic low voltage
VIL
-0.3
Output logic high voltage
VOH
2.4
Output logic low voltage
VOL
-
Input leakage current
IIL
-5
Output leakage current
IOL
-5
Typ
Max
3.3
3.6
3.0
VDD+0.3
0
0.8
-
-
-
0.4
-
5
-
5
Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≤ VOUT ≤ VDD.
Unit
V
V
V
V
V
μA
μA
Note
1
2
IOH = -2mA
IOL = 2mA
3
4
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
5/47