M12L64322A_07 Datasheet, PDF (20/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
3. CAS Interrupt (I)
*Note1
1)Read interrupted by Read (BL=4)
CLK
CMD
ADD
RD RD
A
B
DQ(CL2)
QA0 QB0 QB1 QB2 QB3
DQ(CL3)
tCCD
*Note 2
QA0 QB0 QB1 QB2 QB3
2)Write interrupted by Write (BL=2)
CLK
CMD
ADD
WR WR
tCCD *Note 2
A
B
DQ
DA0 DB0 DB1
tCDL
*Note 3
3)Write interrupted by Read (BL=2)
DQ(CL2)
DQ(CL3)
WR RD
tCCD *Note 2
A
B
DA0
DA0
tCDL
*Note 3
DQ0 DQ1
DQ0 DQ1
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
20/47