M12L64322A_07 Datasheet, PDF (42/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12L64322A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
CLOCK
CKE
CS
1
2
3
4
56
7
8
9
10 11 12 13 14 15 16 17 18 19
tSS
*Note1
*Note3
*Note2
tSS
tSS
RAS
CAS
ADDR
BA1
Ra
Ca
BA0
A10/AP
DQ
Ra
tSHZ
Qa0 Qa1 Qa2
WE
DQM
Precharge
Power-Down
Entry
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Active
Power-down
Exit
Precharge
*Note: 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
: Don't care
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
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