M12L64322A_07 Datasheet, PDF (44/47 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks Synchronous DRAM

ESMT
Mode Register Set Cycle
0
CLOCK
1
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
ADDR
*Note2
*Note1
*Note3
Key
Ra
DQ
HI-Z
WE
DQM
MRS
New
Command
M12L64322A
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
HIGH
tRC
HI-Z
Auto Refresh
New Command
:Don't Care
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision: 2.3
44/47