EN27LN4G08 Datasheet, PDF (7/54 Pages) Eon Silicon Solution Inc. – 4 Gigabit (512M x 8), 3.3 V NAND Flash Memory

EN27LN4G08
Product Introduction
The device is a 4,224Mbit memory organized as 256K rows (pages) by 2,112x8 columns. Spare 64x8
columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to
memory cell arrays accommodating data transfer between the I/O buffers and memory during page read
and page program operations. The program and read operations are executed on a page basis, while
the erase operation is executed on a block basis. The memory array consists of 4096 separately
erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and
allows system upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low.
Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands
require one bus cycle. For example, Reset Command, Status Read Command, etc require just one
cycle bus. Some other commands, like page read and block erase and page program, require two
cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory.
Command Set
Function
1st Cycle
2nd
Cycle
Acceptable Command
during Busy
Read
00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
O
Page Program
80h
10h
Copy-Back Program
85h
10h
Block Erase
Random Data Input ⁽¹⁾
Random Data Output ⁽¹⁾
60h
D0h
85h
-
05h
E0h
Read Status
70h
-
O
Read Status 2
Two-Plane Read ⁽³⁾
F1h
-
O
60h-60h 30h
Two-Plane Read for Copy-Back
Two-Plane Random Data Output ^{(1) (3)}
Two-Plane Page Program ⁽²⁾
Two-Plane Copy-Back Program ⁽²⁾
60h-60h
00h-05h
80h-11h
85h-11h
35h
E0h
81h-10h
81h-10h
Two-Plane Block Erase
60h-60h D0h
Cache Program
80h
15h
Cache Read
31h
-
Read Start For Last Page Cache Read
Two-Plane Cache Read ⁽³⁾
Two-Plane Cache Program ⁽²⁾
3Fh
60h-60h
80h-11h
-
33h
81h-15h
Note:
1. Random Data Input / Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane
Cache Read operation.
This Data Sheet may be revised by subsequent versions
7
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03