EN27LN4G08 Datasheet, PDF (48/54 Pages) Eon Silicon Solution Inc. – 4 Gigabit (512M x 8), 3.3 V NAND Flash Memory

EN27LN4G08
Two-Plane Cache Program
Two-Plane Cache Program is an extension of Cache Program, for a single plane with 2,112 byte data
registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte
data registers enables a simultaneous programming of two pages.
Note:
1. It is noticeable that same row address except for A20 is applied to the two blocks
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
3. Since programming the last page does not employ caching, the program time has to be that of Page
Program. However, if the previous program cycle with the cache data has not finished, the actual
program cycle of the last page is initiated only after completion of the previous cycle, which can be
expressed as the following formula.
tPROG = Program time for the last page + Program time for the (last – 1)^th page
– (Program command cycle time + Last page data loading time)
This Data Sheet may be revised by subsequent versions
48
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/10/03