DS87C530_1 Datasheet, PDF (6/44 Pages) Dallas Semiconductor – EPROM/ROM Micro with Real Time Clock

PLCC TQFP
27, 28 20, 21
2, 11, 4, 6, 7,
13, 14, 33, 34,
40, 41 47
DS87C530/DS83C530
SIGNAL
NAME
RTCX2,
RTCX1
NC
DESCRIPTION
RTCX2, RTCX1 - Timekeeping crystal. A 32.768 kHz crystal
between these pins supplies the time-base for the Real Time
Clock. The device supports both 6 pF and 12.5 pF load
capacitance crystals as selected by an SFR bit described below. To
prevent noise from affecting the RTC, the RTCX2 and RTCX1 pin
should be guard-ringed with GND2.
NC - Reserved. These pins should not be connected. They are
reserved for use with future devices in the family.
COMPATIBILITY
The DS87C530/DS83C530 is a fully static, CMOS 8051-compatible microcontroller designed for high
performance. While remaining familiar to 8051 users, it has many new features. In general, software
written for existing 8051-based systems works without modification on the DS87C530/DS83C530. The
exception is critical timing since the High Speed Micro performs its instructions much faster than the
original for any given crystal selection. The DS87C530/DS83C530 runs the standard 8051 instruction set.
It is not pin-compatible with other 8051s due to the timekeeping crystal.
The DS87C530/DS83C530 provides three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of
direct RAM plus 1 kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with
original 8051 systems. However, timers are individually programmable to run at the new 4 clocks per
cycle if desired. The PCA is not supported.
The DS87C530/DS83C530 provides several new hardware features implemented by new Special
Function Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C530/DS83C530 features a high-speed, 8051-compatible core. Higher speed comes not just
from increasing the clock frequency, but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C530/DS83C530, the same machine cycle takes 4 clocks. Thus the fastest instruction, one machine
cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C530/DS83C530 will see the full 3 to 1 speed improvement.
Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the
original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the
user to eliminate wasted instructions when moving blocks of memory.
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