DS87C530_1 Datasheet, PDF (34/44 Pages) Dallas Semiconductor – EPROM/ROM Micro with Real Time Clock

M2
M1
M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
DS87C530/DS83C530
t_MCS
0
4 t_CLCL
8 t_CLCL
12 t_CLCL
16 t_CLCL
20 t_CLCL
24 t_CLCL
28 t_CLCL
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL
Clock High Time
t_CHCX
Clock Low Time
t_CLCX
Clock Rise Time
t_CLCL
Clock Fall Time
t_CHCL
MIN
10
10
TYP
MAX
5
5
UNITS
ns
ns
ns
ns
NOTES
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
SYMBOL MIN TYP
Serial Port Clock Cycle Time
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Setup to Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Output Data Hold from Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Input Data Hold after Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
Clock Rising Edge to Input Data Valid
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
t_XLXL
t_QVXH
t_XHQX
t_XHDX
t_XHDV
12t_CLCL
4t_CLCL
10t_CLCL
3t_CLCL
2t_CLCL
t_CLCL
t_CLCL
t_CLCL
11t_CLCL
3t_CLCL
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters
as such devices, using the same symbols. For completeness, the following is an explanation of the
symbols.
t Time
L Logic level low
V Valid
A Address
I Instruction
W WR signal
C Clock
D Input data
P PSEN
Q Output data
X No longer a valid logic
level
H Logic level high
R RD signal
Z Tristate
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