DS87C530_1 Datasheet, PDF (24/44 Pages) Dallas Semiconductor – EPROM/ROM Micro with Real Time Clock

DS87C530/DS83C530
A typical application is to select the flag as a reset source. When the Watchdog times out it sets its flag,
which generates reset. Software must restart the timer before it reaches its time-out or the processor is
reset.
Software can select one of four time-out values. Then, it restarts the timer and enables the reset function.
After enabling the reset function, software must then restart the timer before its expiration or hardware
will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected
by a “Timed Access” circuit. This prevents errant software from accidentally clearing the Watchdog.
Time-out values are precise since they are a function of the crystal frequency as shown in Table 8. For
reference, the time periods at 33 MHz also are shown.
The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an
interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source.
The interrupt is independent of the reset. A common use of the interrupt is during debug, to show
developers where the Watchdog times out. This indicates where the Watchdog must be restarted by
software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor
from power saving modes.
The Watchdog function is controlled by the Clock Control (CKCON - 8Eh), Watchdog Control
(WDCON - D8h), and Extended Interrupt Enable (EIE - E8h) SFRs. CKCON.7 and CKCON.6 are WD1
and WD0 respectively and they select the Watchdog time-out period as shown in Table 8.
WATCHDOG TIME-OUT VALUES Table 8
WD1 WD0
INTERRUPT
TIME-OUT
TIME (33 MHz)
0
0
2¹⁷ clocks
3.9718 ms
0
1
2²⁰ clocks
31.77 ms
1
0
2²³ clocks
254.20 ms
1
1
2²⁶ clocks
2033.60 ms
RESET
TIME-OUT
2¹⁷ + 512 clocks
2²⁰ + 512 clocks
2²³ + 512 clocks
2²⁶ + 512 clocks
TIME (33 MHz)
3.9874 ms
31.79 ms
254.21 ms
2033.62 ms
As shown above, the Watchdog Timer uses the crystal frequency as a time base. A user selects one of
four counter values to determine the time-out. These clock counter lengths are 2¹⁷ = 131,072 clocks; 2²⁰ =
1,048,576; 2²³ = 8,388,608 clocks; and 2²⁶ = 67,108,864 clocks. The times shown in Table 8 above are
with a 33 MHz crystal frequency. Once the counter chain has completed a full interrupt count, hardware
will set an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks
left until the reset flag is set. Software can enable the interrupt and reset individually. Note that the
Watchdog is a free running timer and does not require an enable.
There are 5 control bits in special function registers that affect the Watchdog Timer and two status flags
that report to the user. WDIF (WDCON.3) is the interrupt flag that is set at timer termination when there
are 512 clocks remaining until the reset flag is set. WTRF (WDCON.2) is the flag that is set when the
timer has completely timed out. This flag is normally associated with a CPU reset and allows software to
determine the reset source. EWT (WDCON.1) is the enable for the Watchdog Timer reset function. RWT
(WDCON.0) is the bit that software uses to restart the Watchdog Timer. Setting this bit restarts the timer
for another full interval. Application software must set this bit before the time-out. Both of these bits are
protected by Timed Access discussed below. As mentioned previously, WD1 and 0 (CKCON .7 and 6)
select the time-out. The Reset Watchdog Timer bit (WDCON.0) should be asserted prior to modifying the
Watchdog Timer Mode Select bits (WD1, WD0) to avoid corruption of the watchdog count. Finally, the
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