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DS87C530_1 Datasheet, PDF (33/44 Pages) Dallas Semiconductor – EPROM/ROM Micro with Real Time Clock
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DS87C530/DS83C530
MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES
VARIABLE CLOCK
PARAMETER
SYMBOL MIN
MAX
UNITS STRETCH
Data Access ALE Pulse Width
tLHLL2
1.5tCLCL-5
2tCLCL-5
ns
tMCS=0
tMCS>0
Address Hold after ALE Low for
MOVX Write
tLLAX2
0.5tCLCL-5
tCLCL-5
ns
tMCS=0
tMCS>0
RD Pulse Width
WR Pulse Width
tRLRH
tWLWH
2tCLCL-5
tMCS-10
2tCLCL-5
tMCS-10
ns
tMCS=0
tMCS>0
ns
tMCS=0
tMCS>0
RD Low Valid Data In
tRLDV
2tCLCL-20
ns
tMCS=0
tMCS-20
tMCS>0
Data Hold after Read
tRHDX
0
ns
Data Float after Read
ALE Low to Valid Data In
tRHDZ
tLLDV
tCLCL-5
ns
2tCLCL-5
2.5tCLCL-20
ns
tMCS+tCLCL-40
tMCS=0
tMCS>0
tMCS=0
tMCS>0
Port 0 Address to Valid Data In
tAVDV1
3tCLCL-20
ns
tMCS+1.5tCLCL-20
tMCS=0
tMCS>0
Port 2 Address to Valid Data In
tAVDV2
3.5tCLCL-20
ns
tMCS+2tCLCL-20
tMCS=0
tMCS>0
ALE Low to RD or WR Low
tLLWL
0.5tCLCL-5
0.5tCLCL+5
ns
tCLCL-5
tCLCL+5
tMCS=0
tMCS>0
Port 0 Address to RD or WR
Low
tAVWL1
tCLCL-5
2tCLCL-5
ns
tMCS=0
tMCS>0
Port 2 Address to RD or WR
Low
tAVWL2
1.5tCLCL-10
2.5tCLCL-10
ns
tMCS=0
tMCS>0
Data Valid to WR Transition
tQVWX
-5
ns
Data Hold after Write
tWHQX
tCLCL-5
2tCLCL-5
ns
tMCS=0
tMCS>0
RD Low to Address Float
tRLAZ
-0.5tCLCL-5
ns
RD or WR High to ALE High
tWHLH
0
tCLCL-5
10
tCLCL+5
ns
tMCS=0
tMCS>0
NOTE: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the
value of tMCS for each Stretch selection.
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