DS87C530_1 Datasheet, PDF (15/44 Pages) Dallas Semiconductor – EPROM/ROM Micro with Real Time Clock

DATA MEMORY CYCLE STRETCH VALUES Table 4
CKCON.2-0
M2 M1 M0 MEMORY CYCLES
RD OR WR STROBE
WIDTH IN CLOCKS
000
2 (forced internal)
2
001
3 (default external)
4
010
4
8
011
5
12
100
6
16
101
7
20
110
8
24
111
9
28
DS87C530/DS83C530
STROBE WIDTH
TIME @ 33 MHz
60 ns
121 ns
242 ns
364 ns
485 ns
606 ns
727 ns
848 ns
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C530/DS83C530, the standard data pointer is called DPTR, located at SFR addresses 82h and 83h.
These are the standard locations. Using DPTR requires no modification of standard code. The new DPTR
at SFR 84h and 85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location
is the lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user
switches between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the
fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any
activity. Therefore it takes only one instruction to switch from a source to a destination address. Using the
Dual Data Pointer saves code from needing to save source and destination addresses when doing a block
move. The software simply switches between DPTR and 1 once software loads them. The relevant
register locations are as follows.
DPL
82h
DPH
83h
DPL1
84h
DPH1
85h
DPS
86h
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (lsb)
POWER MANAGEMENT
Along with the standard Idle and power-down (Stop) modes of the standard 80C52, the
DS87C530/DS83C530 provides a new Power Management Mode. This mode allows the processor to
continue functioning, yet to save power compared with full operation. The DS87C530/DS83C530 also
features several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation, the DS87C530/DS83C530
uses four clocks per machine cycle. Thus the instruction cycle rate is (Clock/4). At 33 MHz crystal speed,
the instruction cycle speed is 8.25 MHz (33/4). In PMM, the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed
below). The speeds are (Clock/64) and (Clock/1024).
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