DS87C550 Datasheet, PDF (28/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
pin. A 0 in a bit position in either the SETR or the RSTR register disables the corresponding port pin
function. The functionality of the SETR and RSTR registers is shown below.
SETR.7
SETR.6
SETR.5
SETR.4
SETR.3
SETR.2
SETR.1
SETR.0
TGFF1
TGFF0
CMS5
CMS4
CMS3
CMS2
CMS1
CMS0
SETR REGISTER FUNCTIONALITY
This bit toggles if CMPH2:CMPL2 and Timer 2 match and CMTE1 is 1
This bit toggles if CMPH2:CMPL2 and Timer 2 match and CMTE0 is 1
If 1 then P4.5 is set on a match between CMPH0:CMPL0 and Timer 2
If 1 then P4.4 is set on a match between CMPH0:CMPL0 and Timer 2
If 1 then P4.3 is set on a match between CMPH0:CMPL0 and Timer 2
If 1 then P4.2 is set on a match between CMPH0:CMPL0 and Timer 2
If 1 then P4.1 is set on a match between CMPH0:CMPL0 and Timer 2
If 1 then P4.0 is set on a match between CMPH0:CMPL0 and Timer 2
RSTR.7
RSTR.6
RSTR.5
RSTR.4
RSTR.3
RSTR.2
RSTR.1
RSTR.0
CMTE1
CMTE0
CMR5
CMR4
CMR3
CMR2
CMR1
CMR0
RSTR REGISTER FUNCTIONALITY
If 1 then P4.7 toggles on a match between CMPH2:CMPL2 and Timer 2
If 1 then P4.6 toggles on a match between CMPH2:CMPL2 and Timer 2
If 1 then P4.5 is reset on a match between CMPH1:CMPL1 and Timer 2
If 1 then P4.4 is reset on a match between CMPH1:CMPL1 and Time r 2
If 1 then P4.3 is reset on a match between CMPH1:CMPL1 and Timer 2
If 1 then P4.2 is reset on a match between CMPH1:CMPL1 and Timer 2
If 1 then P4.1 is reset on a match between CMPH1:CMPL1 and Timer 2
If 1 then P4.0 is reset on a match between CMPH1:CMPL1 and Timer 2
WATCHDOG TIMER
The free-running watchdog timer, if enabled, will set a flag and cause a reset if not restarted by software
within the user selectable timeout period.
A typical application is to allow the flag to cause a reset. When the watchdog times out, it sets the
Watchdog Timer Reset Flag (WTRF=WDCON.2) which generates a reset if enabled by the Enable
Watchdog Timer Reset (EWT=WDCON.1) bit. In this way if the code execution goes awry and software
does not reset the watchdog as scheduled, the processor is put in a known good state: reset.
In a typical initialization, software selects the desired timeout period using the WD1:0 and the system
clock control bits. Then, it resets the timer and enables the processor reset function. After enabling the
processor reset function, software must then reset the timer before its timeout period or hardware will
reset the CPU. Both the EWT and the Watchdog Reset control (RWT = WDCON.0) bits are protected by
a Timed Access circuit. This prevents errant software from accidentally clearing the watchdog.
The watchdog timer is controlled by the Clock Control (CKCON) and the Watchdog Control (WDCON)
SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the watchdog timeout
period. Of course, the 4X/ 2X (PMR.3) and CD1:0 (PMR.7:6) system clock control bits also affect the
timeout period. Selection of timeout is shown in Table 8.
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