DS87C550 Datasheet, PDF (18/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
faster than wakeup from Idle, and since PMM allows the CPU to continue to execute instructions (even if
doing NOPs), there is little reason to use Idle in new designs.
Switchback
One of the other unique features included on the DS87C550 is Switchback. Simply, Switchback when
enabled will allow serial ports and interrupts to automatically switch back from divide-by-1024 (PMM) to
divide-by-4 (standard speed operation). This feature makes it very convenient to use the Power
Management Mode in real time applications. Of course to return to a divide-by-4 clock rate from divide-
by-1024 PMM, software can simply select the CD1 & CD0 clock control bits to the 4 clocks per cycle
state. However, the DS87C550 provides hardware alternatives for automatic Switchback to standard
speed operation.
The Switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled and
when PMM is selected, there are two possible events that can cause an automatic switchback to divide-
by-4 mode. First, if an interrupt occurs and is set so that it will be acknowledged, this event will cause
the system clock to revert from PMM to divide-by-4 mode. For example, if INT0 is enabled then
Switchback will occur on INT0. However, if INT0 is not enabled, then activity on INT0 will not cause
switchback to occur.
A Switchback can also occur when an enabled UART detects the start bit indicating the beginning of an
incoming serial character or when the SBUF register is loaded initiating a serial transmission. Note that a
serial character’s start bit does not generate an interrupt. This occurs only on reception of a complete
serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in
time for a proper serial reception or transmission. So with Switchback enabled and a serial port enabled,
the automatic switch to normal speed operation occurs automatically in time to receive or transmit a
complete serial character as if nothing special had happened.
Once Switchback causes the processor to make the transition back to divide-by-4 mode, software must
modify SFR bits CD1 & CD0 to re-enter Power Management Mode. However, if a serial port is in the
process of transmitting or receiving a character, then this change back to PMM will not be allowed as the
hardware prevents a write to CD1 & CD0 during any serial port activity.
Since the reception of a serial start bit or an interrupt priority lockout is normally undetectable by
software in an 8051, the Status register features several new flags that are useful. These are described
below.
Status
Information in the Status register assists decisions about switching into PMM. This register contains
information about the level of active interrupts and the activity on the serial ports.
The DS87C550 supports three levels of interrupt priority. These levels are Power-fail, High, and Low.
Status bits STAT.7-5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority;
STATUS.7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority;
STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in
service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority service level before entering PMM. If the current
service level locks out a desired Switchback source, then it would be advisable to wait until this condition
clears before entering PMM.
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