DS87C550 Datasheet, PDF (25/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
output of the prescaler to be passed directly to the pulse generator function (i.e., divide by 1). A value of
FFh passes a clock to the pulse generator function that is the selected prescaler output divided by 256. In
general, the clock generators provide a divide by N+1 selectable repetition rate (i.e., frequency) for their
PWM channel.
Each clock generator has an associated SFR that contains the 8-bit reload value. These registers are called
PW0FG, PW1FG, PW2FG, and PW3FG (see SFR map for addresses). In addition, there is a frequency
generator enable bit (PW0EN, PW1EN, PW2EN, & PW3EN) for each of the clock generator blocks that
must be set to a 1 before these blocks will function. These bits are set to 0 after all resets so software must
set them to 1 to enable the PWM clocks.
The output of the clock generator block is supplied to the input of the pulse generator block.
PWM PULSE GENERATOR
The pulse generator block of the PWM function produces the PWM output signal on device pins
PWMO0 (P6.0), PWMO1(P6.1), PWMO2 (P6.2), AND PWMO3 (P6.3). Each of these output bits has an
enable bit: PW0OE (PW01CON.5), PW1OE (PW01CON.1), PW2OE (PW23CON.5), and PW3OE
(PW23CON.1) that are cleared to 0 on all resets, and must be set to 1 by software before the PWMs will
output a signal.
As described earlier, the pulse generator block is basically a free-running timer with a comparison register
that is loaded with an 8-bit value by software. The value of this register establishes the duty cycle of the
PWM function. The comparison values are stored in SFRs PWM0, PWM1, PWM2, and PWM3 for the
respective PWM channels, and it is these values that determine the pulse duration.
Actually, in accessing these specific SFRs, software has access to both the compare registers and the
timer registers of the pulse generator blocks. When the PWM Timer/Compare Value Select SFR bits
PW0T/C (PW01CON.4), PW1T/C (PW01CON.0), PW2T/C (PW23CON.4), and PW3T/C
(PW23CON.0) are cleared to 0, a read or write to the respective PWMx register accesses the compare
register. When these bits are set to 1, a read or write accesses the timer value. With the use of these bits,
the timers in the pulse generator sections of the PWM functions can be used as general purpose timers if
desired.
When the free-running timer of the pulse generator block rolls over from FFh to 00h, the PWM’s output
is set to a 1. As the timer continues to count up from 0, the output of the PWM is cleared to 0 when the
timer value is equal to the comparison register value. This cycle continues automatically without
processor intervention until software or a reset changes some condition.
The value of 0 in the comparison register is a special case of each PWM function. Rather than allow a set
and a reset of the PWM output bit, special hardware ensures that 0 will be output continuously if 0 is
loaded into the compare register.
There are other SFR bits that affect PWM operation for special modes. Bits PW0DC (PW01CON.6),
PW1DC (PW01CON.2), PW2DC (PW23CON.6), and PW3DC (PW23CON.2) cause the output of the
respective PWM function to be a constant 1. This feature may be useful for driving a fixed DC voltage
into any circuitry attached to the PWM output. Bits PW0F (PW01CON.7), PW1F (PW01CON.3), PW2F
(PW23CON.7), and PW3F (PW23CON.3) are flags that are set by the hardware when the respective
PWM pulse generator timer rolls over from FFh to 0. These flags must be cleared by software to remove
their set condition.
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