DS87C550 Datasheet, PDF (24/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
1, then an A/D Interrupt will only occur if WCM is set (i.e., the A/D result comparison was true). This
feature allows software to respond only to conditions that meet the programmed range.
PULSE WIDTH MODULATION
The DS87C550 contains four independent 8-bit pulse width modulator ( PWMs) functions each with
independently selectable clock sources. For more precise modulation operations, two 8-bit PWM
functions (PWM0 & PWM1 and/or PWM2 & PWM3) can be cascaded together to form a 16-bit PWM
function.
The PWM function is divided into three major blocks: a clock prescaler, a clock generator, and a pulse
generator. A single prescaler provides selectable clocks of different frequencies to each of the four clock
generator blocks. Each clock generator is an 8-bit reloadable counter that determines the repetition rate
(frequency) of its associated PWM. Each pulse generator PWM block is an 8-bit timer clocked by the
clock generator’s output. When this timer reaches zero, the output of the PWM is set to 1. When the timer
reaches the user selected PWM match value stored in SFR PWMx, the PWM output is cleared to 0. In
this way, the frequency and duty cycle of the PWM is varied under software control.
PWM PRESCALER
The prescaler block of the PWM function accepts as a clock input the system clock provided to the CPU
(and other peripherals), and divides it by 1, 4, 16, and 64. Each of these clocks is available at the output
of the prescaler, and is provided to all four of the PWM clock generator blocks. The actual clock used by
the clock generator block is dependant on the setting of SFR bits PWxS2:0 (where x is the PWM channel
number 0-3) located in the PW01CS or PW23CS registers. In addition to selecting one of the prescaler’s
CPU clock divided outputs, setting PWxS2 to a 1 allows an external clock to be used as an input to the
clock generators. The external clocks are input on device pins PWMC0 (P6.4 for PWM0 or PWM1) or
PWMC1 (P6.5 for PWM2 or PWM3). Like all other inputs to the 8051, these inputs are synchronized by
sampling them using the internal machine cycle clock. Therefore these inputs must be of sufficient
duration for the clock to sample them properly (i.e., 2 machine cycles). The complete functionality of the
clock selection SFR bits is as follows:
Prescaler Output
PWxS2:0
Machine Cycle_Clock/1
000
Machine Cycle_Clock/4
001
Machine Cycle_Clock/16
010
Machine Cycle_Clock/64
011
PWMCx (external)
1xx
In determining the exact frequency output of the prescaler, it is important to note that the machine cycle
clock provided to the prescaler is also software-selectable. The machine cycle clock can be the crystal (or
oscillator frequency) divided by 1, 2, 4, or 1024 as determined by the CD1:0 and the 4X/ 2X SFR bits (see
Clock Divide Control section for details).
PWM CLOCK GENERATOR
The clock generator blocks of the PWM modules are pre-loaded by software with an 8-bit value, and this
value determines the frequency or repetition rate of the PWM function. A value of 0 causes the selected
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