DS87C550 Datasheet, PDF (20/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
RING OSCILLATOR
The second enhancement to Stop mode on the DS87C550 allows an additional power saving option while
also making Stop easier to use. This is the ability to start instantly when exiting Stop mode. It is the
internal ring oscillator that provides this feature. This ring can be a clock source when exiting Stop mode
in response to an interrupt. The benefit of the ring oscillator is as follows.
Entering Stop mode turns off the crystal oscillator and all internal clocks to save power. When exiting
Stop mode, the external crystal may require up to 10 ms to begin oscillating again. The DS87C550 can
eliminate that delay through the use of the internal ring oscillator, resuming operation in less than 100 ns
when exiting Stop mode. If a user selects the ring to provide the start-up clock and the processor remains
running, hardware will automatically switch to the crystal once a power-on reset interval (65536 crystal
clocks) has expired.
The ring oscillator runs at approximately 4 MHz but will not be a precise value. Do not conduct real-time
precision operations (including serial communication) during this ring period. The default state is to exit
Stop mode without using the ring oscillator, so action to enable the ring must be taken before entering
stop mode.
The Ring Select (RGSL) bit in the RCON register (RCON.1) controls this function. When RGSL = 1, the
CPU will use the ring oscillator to exit Stop mode quickly. As mentioned above, the processor will
automatically switch from the ring to the crystal after a delay of 65,536 crystal clocks. For a 3.57 MHz
crystal, this is approximately 18 ms. The processor sets a flag called Ring Mode (RGMD = RCON.2) that
tells software that the ring is being used. The bit will be a logic 1 when the ring is in use.
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The Timed Access procedure prevents an errant processor from accidentally altering a bit that
would seriously affect processor operation. The Timed Access procedure requires that the write of a
protected bit be preceded by the following instructions:
MOV 0C7h, #0AAh
MOV 0C7h, #55h
By writing an AAh followed by a 55h to the Timed Access register (location C7h), the hardware opens a
three-cycle window that allows software to modify one of the protected bits. If the instruction that seeks
to modify the protected bit is not immediately preceded by these instructions, the write will not take
effect. The protected bits are:
WDCON.6 POR Power-On Reset Flag
WDCON.3 WDIF Watchdog Interrupt Flag
WDCON.1 EWT Watchdog Reset Enable
WDCON.0 RWT Reset Watchdog Timer
RCON.0 BGS Band-Gap Select
ROMSIZE.2 RMS2
Program Memory Select
Bit 2
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