DS87C550 Datasheet, PDF (17/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
The oscillator-fail detect circuitry is enabled by software setting the enable bit OFDE (PCON.4) to a 1.
Please note that software must use a “Timed Access” procedure (described later) to write to this bit. There
is an oscillator-fail detect flag, OFDF (PCON.5), that is set to a 1 by the hardware when it detects an
oscillator failure. The processor will be forced into a reset state when this occurs if enabled by OFDE.
The oscillator-fail detect flag can only be cleared to a 0 by a power-up reset or by software. It should be
noted that the oscillator-fail detect circuitry is not disabled by entering Stop mode. There fore, the user
must ensure that this feature is disabled before entering Stop mode.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. Normally, during default operation, the DS87C550
uses 4 clocks per machine cycle. Thus the instruction cycle (machine cycle clock) rate is Clock/4. At 33
MHz crystal speed, the instruction cycle speed is 8.25 MHz. In PMM the microcontroller operates, but
from an internally divided version of the clock source. This creates a lower power state without external
components. As shown in Figure 3, the system clock may be selected to use the crystal (or external
oscillator) frequency divided by 256. This produces a machine cycle that consists of the crystal frequency
divided by 1024, which is considered Power Management Mode (PMM). With the processor executing
instructions at this much lower rate, a significant amount of power is saved.
Software is the only mechanism to invoke the PMM. Table 6 illustrates the instruction cycle rate in
PMM for several common crystal frequencies. Since power consumption is a direct function of operating
speed, PMM runs very slowly and provides the lowest power consumption without stopping the CPU.
This is illustrated in Table 7.
MACHINE CYCLE RATE Table 6
Full Operation
Crystal Speed (4 clocks per machine cycle)
PMM
(1024 clocks per machine cycle)
11.0592 MHz 2.765 MHz
10.8 kHz
16 MHz
4.0 MHz
15.6 kHz
25 MHz
6.25 MHz
24.4 kHz
33 Mhz
8.25 MHz
32.2 kHz
OPERATING CURRENT ESTIMATES IN PMM Table 7
Full Operation
PMM
Crystal Speed (4 clocks per machine cycle) (1024 clocks per machine cycle)
11.0592 MHz 13.1 mA
4.8 mA
16 MHz
17.2 mA
5.6 mA
25 MHz
25.7 mA
7.0 mA
33 Mhz
32.8 mA
8.2 mA
Note that PMM provides a lower power condition than Idle mode. This is because in Idle, all clocked
functions such as timers run at a rate of crystal divided by 4. Since wakeup from PMM is as fast as or
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