DS87C550 Datasheet, PDF (14/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
Another useful feature of the device is its ability to automatically switch the active data pointer after a
DPTR-based instruction is executed. This feature can greatly reduce the software overhead associated
with data memory block moves, which toggle between the source and destination registers. When the
Toggle Select bit (TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of
the following DPTR related instructions are executed:
§ INC DPTR
§ MOV DPTR, #data16
§ MOVC A, @A+DPTR
§ MOVX A, @DPTR
§ MOVX @DPTR, A
As a brief example, if TSL is set to 1, then both data pointers can be updated with the two instruction
series shown.
INC DPTR
INC DPTR
With TSL set, the first increment instruction increments the active data pointer, and then causes the SEL
bit to toggle making the other DPTR active. The second increment instruction increments the newly
active data pointer and then toggles SEL to make the original data pointer active again.
CLOCK CONTROL and POWER MANAGEMENT
The DS87C550 includes a number of unique features that allow flexibility in selecting system clock
sources and operating frequencies. To support the use of inexpensive crystals while allowing full-speed
operation, a clock multiplier is included in the processor’s clock circuit. Also, along with the Idle and
power-down (Stop) modes of the standard 80C52, the DS87C550 provides a new Power Management
mode. This mode allows the processor to continue instruction execution at a very low speed to
significantly reduce power consumption (below even idle mode). The DS87C550 also features several
enhancements to Stop mode that make this extremely low power mode more useful. Each of these
features is discussed in detail below.
SYSTEM CLOCK CONTROL
As mentioned previously, the DS87C550 contains special clock control circuitry that simultaneously
provides maximum timing flexibility and maximum availability and economy in crystal selection. There
are two basic functions to this circuitry: a frequency multiplier and a clock divider. By including a
frequency multiplier circuit, full-speed operation of the processor may be achieved with a lower
frequency crystal. This allows the user the ability to choose a more cost-effective and easily obtainable
crystal than would be possible otherwise.
The logical operation of the system clock divide control function is shown in Figure 3. The clock signal
from the crystal oscillator (or external clock source) is provided to the frequency multiplier module, to a
divide-by-256 module, and to a 3-to-1 multiplexer. The output of this multiplexer is considered the
system clock. The system clock provides the time base for timers and internal peripherals, and feeds the
CPU State Clock Generation circuitry. This circuitry divides the system clock by 4, and it is the four
phases of this clock that make up the instruction execution clock. The four phases of a single instruction
execution clock are also called a single machine cycle clock. Instructions in the DS87C550 all use the
machine cycle as the fundamental unit of measure and are executed in from one to five of these machine
cycles. It is important to note the distinction between the system clock and the machine cycle clock as
they are often confused, creating errors in timing calculations. In performing timing calculations, it is
14 of 50