DS87C550 Datasheet, PDF (27/50 Pages) Dallas Semiconductor – EPROM High-Speed Micro with A/D and PWM

DS87C550
When the LSB of timer/counter 2 (TL2) overflows, flag TF2B (T2SEL.4) is set, and flag TF2 (T2CON.7)
is set when the high byte (TH2) overflows. Setting flag TF2 also sets flag TF2B. Even though only one
interrupt is available for Timer 2, either or both of these overflows can be programmed to request an
interrupt. To enable the interrupt, the Timer 2 interrupt enable bit ET2 (EIE.7) must be set to a 1. The 8-
bit overflow interrupt or the 16-bit overflow interrupt is then individually enabled by setting TF2BS
(T2SEL.6) or TF2S (T2SEL.7). Since there is only one interrupt vector for both possible Timer 2
interrupts, the interrupt service routine must determine which event caused the interrupt by polling the
available flags. For both interrupt flags, software must clear them upon servicing the interrupt. There is
no automatic hardware clearing of these flags.
TIMER 2 CAPTURE FEATURE
One of the new features added to Timer 2 is the capture function. The output of Timer 2 is available to
four independent 16-bit capture register pairs (CPTH3:CPTL3, CPTH2:CPTL2, CPTH1:CPTL1, &
CPTH0:CPTL0). These registers are loaded with the 16-bit value contained in Timer 2 when transitions
occur on the corresponding input pin INT5/CT3, INT4/CT2, INT3/CT1 or INT2/CT0 (P1.3, P1.2, P1.1,
or P1.0) respectively. When the capture function is not being used, these input pins also serve as external
interrupt inputs. The Capture Trigger Control register (CTCON) can be programmed to make the capture
occur on a rising edge, a falling edge, or on either a rising or a falling edge on these input pins. The
functionality of the CTCON register is illustrated below. Note that the edge sensitivity established by the
setting of CTCON bits applies to both the capture function and the external interrupt function of these
input pins. This addition allows maximum flexibility in selecting interrupt polarity. Whether these input
pins are used as external interrupt inputs or as capture commands, the input will set the appropriate flag in
the External Interrupt Flag register (T2IR.3:0) and will create an interrupt if the associated enable in the
Extended Interrupt Enable (EIE.3:0) register is set.
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
CTCON REGISTER FUNCTIONALITY
CT3
Capture register 3 triggered by a falling edge on INT5/CT3
CT3
Capture register 3 triggered by a rising edge on INT5/CT3
CT2
Capture register 2 triggered by a falling edge on INT4/CT2
CT2
Capture register 2 triggered by a rising edge on INT4/CT2
CT1
Capture register 1 triggered by a falling edge on INT3/CT1
CT1
Capture register 1 triggered by a rising edge on INT3/CT1
CT0
Capture register 0 triggered by a falling edge on INT2/CT0
CT0
Capture register 0 triggered by a rising edge on INT2/CT0
TIMER 2 COMPARE FEATURE
Another new feature added to Timer 2 capabilities is the compare function. Prior to enabling this
function, the associated compare register pair (CMPH0:CMPL0, CMPH1:CMPL1, CMPH2:CMPL2) is
loaded by software with a 16-bit number. Each time Timer 2 is incremented, the contents of these
registers are compared with the new value of the timer. When a match occurs, the corresponding interrupt
flag (T2IR.6:4) is set to a 1 on the next machine cycle and an interrupt will occur if the corresponding
enable bit is set in the Extended Interrupt Enable (EIE.6:4) register. When a match with CMPH0:CMPL0
occurs, port pins P4.0 through P4.5 are set to a 1 if the corresponding bits of the Set Enable register
(SETR) are at logic 1. If the match is with CMPH1:CMPL1, port pins P4.0 through P4.5 are reset to 0
when the corresponding bits in the reset/toggle enable register RSTR are at logic 1. A match with
CMPH2:CMPL2 toggles port pins P4.6 and 4.7 if the corresponding bits in the RSTR register are at logic
1. Note that for the toggle function it is not the port pin latch that is actually toggled. Instead, separate
flip-flops output the SFR bits TGFF1 and TGFF0 that actually determine the state of the respective port
27 of 50