LUPA-4000 Datasheet, PDF (37/49 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Data Sheet
Pad Pin Pin Name
29
Q7
dec_y_load
30
R3
vdd
31
M3
gndd
32 L2
prebus1
33 L3
prebus2
34
Q8
sh_col
35
R4
pre_col
36
R5
norowsel
37
R6
clock_y
38
R7
sync_y
39
K2
eos_y_r
40
Q9
temp_diode_p
41
Q10 temp_diode_n
42
R8
vpix
43
R9
vmem_l
44
R10 vmem_h
45
R11 vres
46
Q11 vres_ds
47 R12 ref_low
48 Q12 linear_conv
49 P15 bit_9
50 Q14 bit_8
51 Q15 bit_7
52 R13 bit_6
53 R14 bit_5
54 R15 bit_4
55 P14 bit_3
56 Q13 bit_2
57 R16 bit_1
58 Q16 bit_0
59 P16 clock
60 N14 gndd
61 N15 vddd
62 L16 gnda
63 L15 vdda
64 N16 bit_inv
65 M16 CMD_SS
66 L14 analog_in
67 M15 CMD_FS
Pin Type Description
Input
Analog reference input. Biasing for Y-addressing.
Connect with R=2MΩ to Vdd and decouple with
C=100nF to gndd.
Supply Power supply digital modules.
Ground Ground digital modules.
Input
Digital input. Control signal to reduce readout time.
Input
Digital input. Control signal to reduce readout time.
Input
Digital input. Control signal of the column readout.
Input
Digital input. Control signal of the column readout to
reduce row-blanking time.
Input
Digital input. Control signal of the column readout.
Input
Digital input. Clock of the Y-addressing.
Input
Digital input. Synchronises the Y-address register.
Testpin
Indicates when the end of frame is reached when
scanning in the ‘right’ direction.
Testpin Anode of temperature diode.
Testpin Cathode of temperature diode.
Supply Power supply pixel array.
Supply Power supply Vmem drivers.
Supply Power supply Vmem drivers.
Supply Power supply reset drivers.
Supply Power supply reset drivers.
Input
Analog reference input. Low reference voltage of ADC.
(see figure 7 for exact resistor value)
Input
Digital input. 0= linear conversion; 1= gamma
correction.
Output Digital output 1 <9> (MSB).
Output Digital output 1 <8>.
Output Digital output 1 <7>.
Output Digital output 1 <6>.
Output Digital output 1 <5>.
Output Digital output 1 <4>.
Output Digital output 1 <3>.
Output Digital output 1 <2>.
Output Digital output 1 <1>.
Output Digital output 1 <0> (LSB).
Input
ADC clock input.
Supply Digital GND of ADC circuitry.
Supply Digital supply of ADC circuitry (nominal 2.5V).
Supply Analog GND of ADC circuitry.
Supply Analog supply of ADC circuitry (nominal 2.5V).
Input
Digital input. 0=no inversion of output bits; 1 =
inversion of output bits.
Input
Input
Analog reference input. Biasing of second stage of ADC.
Connect to VDDA with R=50kΩ and decouple with
C=100 nF to GNDa.
Analog input of 1^st ADC.
Input
Analog reference input. Biasing of first stage of ADC.
Connect to VDDA with R=50kΩ and decouple with
C=100 nF to GNDa.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05712 Rev.**(Revision 1.2 )
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