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LUPA-4000 Datasheet, PDF (16/49 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor
LUPA-4000
Data Sheet
3.6.1 ADC timing
The ADC converts the pixel data on the falling edge of the ADC_CLOCK but it takes 2
clock cycles before this pixel data is at the output of the ADC. This pipeline delay is
shown in Figure 6.
Figure 6: ADC timing
3.6.2 Setting of the ADC reference voltages
2.5V
RHIGH_ADC
REF_HIGH ~ 2 V
RADC
external
internal
REF_LOW ~ 1 V
external
RLOW_ADC
Figure 7: In- and external ADC connections
The internal resistor RADC has a value of approximately 300 Ω.
This results in the values for the external resistors:
Resistor
RADC_VHIGH
RADC
RADC_VLOW
Value (Ω)
75
300
220
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San Jose, CA 95134
408-943-2600
Contact: info@Fillfactory.com Document #: 38-05712 Rev.**(Revision 1.2 )
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