LUPA-4000 Datasheet, PDF (27/49 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Data Sheet
4.1 Timing of the pixel array
The first part of the timing is related with the timing of the pixel array. This implies
the control of the integration time, the synchronous shutter operation and the sampling
of the pixel information onto the memory element inside each pixel. The signals
needed for this control are described in the previous paragraph 3.9 and in figure 10.
Figure 13 shows the external applied signals required to control the pixel array. At
the end of the integration time from frame I+1, the signals Mem_hl, Precharge and
Sample have to be given. The reset signal controls the integration time, which is
defined as the time between the falling edge of reset and the rising edge of sample.
Figure 13: Timing of the pixel array: The integration time is determined by the falling edge of the
reset pulse. The longer the pulse is high, the shorter the integration time. At the end of the integration
time, the information has to be stored onto the memory element for readout.
Timing specifications for each signal are:
Table 12: Timing specifications
Symbol Name
Value
a
Mem_HL
5 – 8,2
µsec
b
Precharge
3 – 6 µsec
c
Sample
5 – 8 µsec
d
Precharge-Sample > 2 µsec
e
Integration time
> 1 µsec
Falling edge of Precharge is equal or later than falling edge of Vmem.
Sample is overlapping with precharge.
Rising edge of Vmem is more than 200nsec after rising edge of Sample.
Rising edge of reset is equal or later than rising edge of Vmem.
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