LUPA-4000 Datasheet, PDF (15/49 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Data Sheet
3.5 Column amplifiers
The column amplifiers are designed for minimum power dissipation and minimum
loss of signal for this reason multiple biasing signals are needed.
The column amplifiers also have the “voltage-averaging” feature integrated. In case
of voltage averaging mode, the voltage average between 2 columns is taken and read
out. In this mode only 2:1 pixels have to be read out.
To achieve the voltage-averaging mode, an additional external digital signal called
“voltage-averaging” is required in combination with a bit from the SPI.
3.6 Analog to Digital Converter
The LUPA4000 has a two 10 bit flash analog digital converters running nominally at
33 Msamples/s. The ADC’s are electrically separated from the image sensor. The
inputs of the ADC should be tied externally to the outputs of the output amplifiers.
One ADC will sample the even columns and the other one will sample the odd
columns. Although the input range of the ADC is between 1V and 2V and the output
range of the analog signal is only between 0.3V and 1.3V, the analog output and
digital input may be tied to each other directly. This is possible because there is an on
chip level-shifter located in front of the ADC to lift up the analog signal to the ADC
range.
Table 6: ADC specifications
Parameter
Input range
Quantization
Nominal data rate
DNL (linear conversion mode)
INL (linear conversion mode)
Input capacitance
Power dissipation @ 33 MHz
Conversion law
Specification
1 – 2V (*)
10 Bits
33 Msamples/s
Typ. < 0.4LSB RMS
Typ. < 3.5 LSB
< 2 pF
50 mW
Linear / Gamma-corrected
(*): The internal ADC range will be typ. 50mV lower then the external applied
ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal
resistors in the ADC.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05712 Rev.**(Revision 1.2 )
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