LUPA-4000 Datasheet, PDF (23/49 Pages) Cypress Semiconductor – 4M Pixel CMOS Image Sensor

LUPA-4000
Data Sheet
Figure 10: Internal timing of the pixel. Levels are defined by the pixel array voltage supplies (For
the correct polarities of the signals refer to table 11).
The signals in figure 10 are generated from the on chip drivers. These on chip drivers
need 2 types of signals to generate the exact type of signal. It needs digital control
signals between 0 and 3.3V (internally converted to 2.5V) with normal driving
capability and power supplies. The control signals are required to indicate the
moment they need to occur and the power supplies indicate the level.
Vmem is made of a control signal Mem_hl and 2 supplies Vmem_h and Vmem_l. If
the signal Mem_hl is the logic “0” than the internal signal Vmem is low, if Mem_hl is
logic “1” the internal signal Vmem is high.
Reset is made by means of 2 control signals: Reset and Reset_ds and 2 supplies: Vres
and Vres_ds. Depending on the signal that becomes active, the corresponding supply
level is applied to the pixel.
Table 11 summarizes the relation between the internal and external pixel array
signals.
Table 11: Overview of the in- and external pixel array signals
Internal Signal
Vlow
Precharge
Sample
Reset
Vmem
AH: Active High
AL: Active Low
0
0
0
2.0– 2.5V
Vhigh
0.45V
2.5V
2.5 – 3.3V
2.5-3.3V
External
control signal
Precharge
(AL)
Sample (AL)
Reset (AH) &
Reset_ds (AH)
Mem_hl (AL)
Low DC-
level
Vpre_l
Gnd
Gnd
Vmem_l
High DC-level
Controlled by
bias-resistor
Vdd
Vres &
Vres_ds
Vmem_h
In case the dual slope operation is desired, one needs to give a second reset pulse to a
lower reset level during integration. This can be done by the control signal Reset_ds
and by the power supply Vres_ds that defines the level to which the pixel has to be
reset.
Note that Reset is dominant over Reset_ds, which means that the high voltage level
will be applied for reset, if both pulses occur at the same time.
Note that multiple slopes are possible having multiple Reset_ds pulses with a lower
Vres_ds level for each pulse given within the same integration time.
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San Jose, CA 95134
408-943-2600
Contact: [e-mail] Document #: 38-05712 Rev.**(Revision 1.2 )
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