STC3500 Datasheet, PDF (9/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Detailed Description continued
Operating Modes: The STC3500 operates in either Free Run, locked, or Hold Over mode:
Free Run – In Free Run mode, Sync_Clk, Sync_8K, BITS_Clk, and Sync_2K, the output clocks, are determined
directly from and have the accuracy of the calibrated free running OCXO/TCXO. Reference inputs continue to be
monitored for signal presence and frequency offset, but are not used to synchronize the outputs.
Locked – The Sync_Clk, Sync_8K, BITS_Clk, and Sync_2K outputs are phase locked to and track the selected input
reference. Upon entering the Locked mode, the device begins an acquisition process that includes reference
qualification and frequency slew rate limiting, if needed. Once satisfactory lock is achieved, the “Locked” bit is set in the
DPLL_Status register, and a frequency history for the selected reference will begin to be compiled. When a usable
Hold Over history has been established, the Hold_Avail pin is set, and the “Hold Over Available” bit is set in the
DPLL_Status register.
Phase comparison and phase lock loop filtering operations in the STC3500 are completely digital. As a result, device
and loop behavior are entirely predictable, repeatable, and extremely accurate. Carefully designed and proven
algorithms and techniques ensure completely hit-less reference switches, operational mode changes, and master/slave
switches.
Basic loop bandwidth is programmable from .66 milliHertz to 1.4 Hertz, giving the user a wide range of control over the
system response.
When a new reference is acquired, maximum frequency slew limits ensure smooth frequency changes. Once lock is
achieved, (<100 seconds for stratum) the “Locked” bit is set. If the STC3500 is unable to maintain lock, Loss of
Lock (LOL) is asserted. All transitions between locked, Hold Over and Free Run modes are performed with no
phase hit and smooth frequency and phase transitions.
Reference phase hits or phase differences encountered when switching references (or when entering locked mode) are
nulled out with an automatic phase build-out function, with a residual phase error of less than 1 nS. The optional Phase
build-out feature can be disabled for phase hits on the selected reference, as required for Stratum 3.
Hold Over – Upon entering Hold Over mode, the Sync_Clk, Sync_8K, BITS_Clk, and Sync_2K outputs are
determined from the Hold Over history established for the last selected reference. Output frequency is determined by a
weighted average of the Hold Over history, and accuracy is determined by the OCXO/TCXO. Hold Over mode may be
entered manually or automatically. Automatic entry into Hold Over mode occurs when operating in the automatic mode,
the reference is lost, and no other valid reference exists. The transfer into and out of Hold Over mode is designed to be
smooth and free of hits. The frequency slew is also limited to a maximum of ±2 ppm/sec.
The history accumulation algorithm uses a first order frequency difference filtering algorithm. Typical Hold Over
accumulation takes about 15 minutes. When a usable Hold Over history has been established, the Hold_Avail pin is
set, and the “Hold Over Available” bit is set in the DPLL_Status register. The Hold Over history continues to be
updated after “Hold Over Available” is declared.
The Hold Over history accumulates only when it has locked on either an external reference in Master operation or the
Xref clock in Slave operation, starting 15 minutes after power up. Tracking will be suspended automatically when
switching to a new reference, while in the Hold Over mode, and in the Free Run mode. A set of registers allows the
application to control a Hold Over history maintenance policy, enabling either a rebuild or continuance of the history
when a reference switch occurs.
Furthermore, under register access control, a backup Hold Over history register is provided. It may be loaded from the
active Hold Over history or restored to the active Hold Over history. The active Hold Over history may also be flushed.
See Hold Over History Accumulation and Maintenance section.
Hold Over mode may be entered at any time. If there is no Hold Over history available, the prior output frequency will
be maintained. When in Hold Over, the application may read (via register access) the time since Hold Over was
entered.
Preliminary Data Sheet: TM060 Page 9 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice