STC3500 Datasheet, PDF (42/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Application Notes continued
Set the device bandwidth and enable/disable phase build-out by writing the appropriate values to the Bandwidth_PBO
register, 0x03. (See Register Descriptions and Operation). The recommended value is .098 Hz. for Stratum 3.
Select 50% duty cycle or variable pulse width for the Sync_8K and Sync_2K output by writing the appropriate values
to bits 4 and 5 of the Ctl_Mode register (0x04), as shown below:
Pulse Width Control
Sync_2K and Sync_8K 50% duty cycle
Sync_2K 50% duty cycle, Sync_8K variable pulse width
Sync_2K variable pulse width, Sync_8K 50% duty cycle
Sync_2K and Sync_8K variable pulse width
Reg. 0x03 BITS 5-4
00
01
10
11
In variable pulse width mode, the desired pulse width is written to register FR_Pulse_Width (0x10). The pulse width is
the register value (valid range is 1 - 15) multiple of the Sync_Clk clock period. The same pulse width is applied to both
Sync_8K and Sync_2K. For example, if Sync_Clk is at 19.44 MHz and the desired pulse width is 206nS, write
FR_Pulse_Width to 0000 0100 (4 x 51.5nS).
The auto-detected input reference frequencies may be read from bits 7-4 of the Ref(1-8)_Frq_Priority registers.
If desired, write the Freerun_Priority register (0x24) to enable Free Run to be treated like a reference (See Register
Descriptions and Operation section). If it is enabled, set the desired priority and revertivity.
Select the desired operational mode and reference by writing the appropriate value to register Op_Mode (0x05).
Mode
Free Run
Lock on Ref1
Lock on Ref2
Lock on Ref3
Lock on Ref4
Lock on Ref5
Lock on Ref6
Lock on Ref7
Lock on Ref8
Hold Over
Reg. 0x03
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
Preliminary Data Sheet: TM060 Page 42 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice