STC3500 Datasheet, PDF (18/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Register Descriptions and Operation
Chip_ID_low, 0x00 (R)
Low byte of chip ID: 0x12
Bit 7 ~ Bit 0
Chip_ID_High, 0x01 (R)
High byte of chip ID: 0x30
Bit 7 ~ Bit 0
Chip_Revision, 0x02 (R)
Bit 7 ~ Bit 0
Chip revision number: Chip revision number is subject to change.
Bandwidth, 0x03 (R/W)
Bit 7 ~ Bit 4
Bit 3 ~ Bit 0
Reserved
Bandwidth Selection in Hz:
0000 - 0101: 0.025
0110: 0.049
0111: 0.098 (Reset Default)
1000: 0.20
1001: 0.39
1010: 0.78
1011 - 1111: 1.6
Bits 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is .098 Hz.
Ctl_Mode, 0x04 (R/W)
Bit 7 ~ Bit 6
Bit 5
Reserved
Synk 2K 2 kHz
Pulse width
control:
0: 50%
1: Controlled by
FR_Pulse_Width
register
Default: 0
Bit 4
Sync 8K 8 kHz
Pulse width
control:
0: 50%
1: Controlled by
FR_Pulse_Width
register
Default: 0
Bit 3
BITS Clock
Output
Frequency:
1: 1.544 MHz
0: 2.048 MHz
(read only)
Bit 2
HM Ref:
1: Sel0-3 pin
control of op
mode/ref
0: Register control
of op model/ref
(read only)
Bit 1
Active
Reference
Selection:
1: Manual
0: Automatic
Default: 1
Bit 0
Input Reference
Frequency
Selection:
1: Manual
0: Automatic
Default: 0
When bit 0 is reset (automatic frequency selection), bits 4 - 7 of the Ref_Frq_Priority registers become read-only. When bit 1 is
reset (automatic reference and mode selection), bits 3 - 0 of the Op_Mode register become read-only.
The power-up default control mode is Bits 0, 4 and 5 = 0, manual reference and automatic reference frequency selection, and 50%
duty cycle on Sync_8K and Sync_2K.
When HM_Ref = 1, enabling hardware control of reference selection, bit 1 of this register is read-only and = 1.
Bits 2 and 3 are always read-only.
Preliminary Data Sheet: TM060 Page 18 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice