STC3500 Datasheet, PDF (25/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Register Descriptions and Operation continued
Chksum, 0x33 (R)
Reserved
Bit 7 ~ Bit 1
Bit 0
Configuration Data checksum
pass/fail indicator:
0 = fail, 1 = pass
Checksum verification register for configuration data. See Application Notes, Configuration Data section. Initialized to zero on
power-up/reset, indicates 0 = fail or 1 = pass upon configuration data pump completion.
EE_Mode, 0x36 (R/W)
Reserved
Bit 7 ~ Bit 1
Bit 0
EEPROM write enable:
0 = disabled, 1 = enabled
EEPROM write enable register. See Application Notes, General, Reading and Writing EEPROM Data section.
EE_Cmd, 0x37 (R, W)
Bit 7
EEPROM read/write
ready bit:
0 = not ready
1 = ready
Bit 6 ~ Bit 2
Reserved
Bit 1 ~ 0
EEPROM read/write command bits:
00: Reset FIFO
01 = Write command
10 = Read command
EEPROM read/write command register. See Application Notes, General, Reading and Writing EEPROM Data section.
EE_Page_Num, 0x38 (R, W)
Bit 7 ~ Bit 0
EEPROM read/write page number, 0x00 to 0x9f (0 - 159)
EEPROM read/write page number register. EEPROM consists of 160 pages. See Application Notes, General, Reading and
Writing EEPROM Data section.
EE_FIFO_Port, 0x39 (R, W)
EEPROM read/write FIFO data
Bit 7 ~ Bit 0
EEPROM read/write FIFO port register. EEPROM data is written to/read from here. See Application Notes, General, Reading
and Writing EEPROM Data section.
Preliminary Data Sheet: TM060 Page 25 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice