STC3500 Datasheet, PDF (33/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Application Notes continued
The path lengths of the two Sync_8K or Sync_Clk to Xref signals is of interest, however. They need not be the same.
However, to accommodate path length delays, the STC3500 provides a programmable phase skew feature, which
allows the application to offset the output clocks from the cross-reference signal by up to ±32 ns, in 0.25nS increments.
This offset may therefore be programmed to exactly compensate for the actual path length delay associated with the
particular application’s cross-reference traces. The offset may further be adjusted to accommodate any output clock
distribution path delay differences. Phase offset is programmed by writing to the Phase_Offset register, and is typically
a one-time device initialization function. (See register description and Register Access Control sections). Thus,
master/slave switches with the STC3500 devices may be accomplished with near-zero phase hits.
For applications that use Hardware Control only (i.e. phase offset programming is not available), it is desirable to keep
the cross couple path lengths at a minimum and relatively equal in length, as the path length will appear as a phase hit
in the slave clock output when a master/slave switch occurs in a Hardware Control configuration.
Master / Slave Configuration
Figure 10
Reference 1 In
Reference n In
Ref1
STC3500
1
Sync_2K
Ref_Sn_TC3SB5yI0^TnS_{0c__CCllkk}
Sync_8K
Xref (8 kHz)
2 kHz multi-frame sync
BITS clock output
Synchronized clock output
8 kHz
Xref
(8 kHz)
Ref1
Sync_8K
Sync_Clk
BITS_Clk
Sync_2K
STC3500
Refn
2
8 kHz
Synchronized clock output
BITS clock output
2 kHz multi-frame sync
Master/Slave Operation and Control – The Master/Slave state is always manually controlled by the application.
Master or slave state of a device is determined by the M/S pin. Choosing the master/slave states is a function of the
application, based on the configuration of the rest of the system and potential detected fault conditions.
When operating in Hardware Control or Register Access Manual Control mode, it is important to set the slave reference
selection the same as the master to ensure use of the same reference when/if the slave becomes master. In Register
Access Manual Control mode, the Ref_Mask register should also be written to the same value for both devices.
Master/slave switches should be performed with minimal delay between switching the states of each of the two devices.
This can be easily accomplished, for example, by controlling the master/slave state with a single signal, coupled to one
of the devices through an inverter.
In the case of Register Access Automatic Control mode, where reference selection is automatic, it is necessary to read
the operational mode (bits 3-0) from the master’s Op_Mode register and write it to the slave’s Op_Mode register. The
master’s reference selection will then be used by the slave when it becomes master. In addition to having the
references populated
the same, and in the same order for both devices, it is desireable to write the reference frequency and priority registers
Ref(1-8)_Frq_Priority and the Ref_Mask registers to the same values for both devices to ensure seamless master/
slave switches.
Reset – Device reset is an initialization time function, which resets internal logic and register values. A reset is
performed automatically when the device is powered up. Registers return to their default values, as noted in the register
descriptions. Device mode and functionality following a reset are determined by the state of the various hardware
control pins.
Preliminary Data Sheet: TM060 Page 33 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice