STC3500 Datasheet, PDF (44/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Application Notes continued
Register Access Automatic Control
For Register Access Automatic Control, the interfaces, reset, and bus operations are the same as shown in Figure 12
and described in the Register Access Manual Control section. The Bandwidth_PBO register write operation is also
the same.
The BITS clock output frequency is selected by the BITS_Sel pin. When BITS_Sel = 1, the BITS frequency is 1.544
MHz and when BITS_Sel = 0, the BITS frequency is 2.048 MHz
Reset may be pulled low for a minimum of 100nS during chip start-up (or any other desired time) to initialize the full
device state.
Following any reset, device configuration data must be pumped, either automatically from the external EEPROM, or by
the application through the bus interface (see Application Notes, General, Configuration Data section). Tie Dmode
“High” for EEPROM pump, and “Low” for register pump.
If the optional EEPROM is equipped, EEPROM data may be read or written via the bus interface. See Application
Notes, General, Reading and Writing EEPROM section.
Select automatic active reference selection by writing bit 1 of the register Ctl_Mode (0x04) to 0. The auto-detected
input reference frequencies may be read from bits 7-4 of the Ref(1-8)_Frq_Priority registers. With automatic reference
selection, the device (In master mode) also performs operational mode selection (Locked, Hold Over, and Free Run)
automatically, as shown in Figure 8.
Individual references may be enabled or disable for use by writing the appropriate values to the Ref_Mask (0x0b) register.
Select 50% duty cycle or variable pulse width for the Sync_8K and Sync_2K output by writing the appropriate values
to bits 4 and 5 of the Ctl_Mode register (0x04), as shown below:
Pulse Width Control
Sync_2K and Sync_8K 50% duty cycle
Sync_2K 50% duty cycle, Sync_8K variable pulse width
Sync_2K variable pulse width, Sync_8K 50% duty cycle
Sync_2K and Sync_8K variable pulse width
Reg. 0x03 BITS 5-4
00
01
10
11
In variable pulse width mode, the desired pulse width is written to register FR_Pulse_Width (0x10). The pulse width is
the register value multiple (valid range is 1 - 15) of the Sync_Clk clock period. The same pulse width is applied to both
Sync_8K and Sync_2K. For example, if Sync_Clk is at 19.44 MHz and the desired pulse width is 206nS, write
FR_Pulse_Width to 0000 0100
(4 x 51.5nS).
Preliminary Data Sheet: TM060 Page 44 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice