STC3500 Datasheet, PDF (12/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Detailed Description continued
Register Control – Bus/Register access is available in 8-bit parallel or SPI form, as selected by the Bmode pin. Bmode=1
selects parallel bus access, and Bmode=0 selects SPI. Parallel bus and SPI data I/O operations are shown as follows.
Parallel Bus Timing, Read Access
Figure 3
CS
t_CA
t_ALE
t_AR
ALE
t_RWs
t_RWh
R/W
RDY
t_CR
AD
t_As
t_Ah
Address
t_RDY
t_RC
t_CR
t_RDs
t_RDh
Read Data
Parallel Bus Timing, Write Access
Figure 4
CS
ALE
R/W
t_CA
t_ALE
t_AR
t_RWs
t_RWh
RDY
t_CR
AD
t_As
t_Ah
Address
t_RDY
t_RC
t_CR
t_WDs t_WDh
WriteData
Symbol
t_CA
t_ALE
t_AR
t_RWs
t_RWh
t_RDY
t_RC
t_CR
t_As
t_Ah
t_RDs
t_RDh
t_WDs
t_WDh
Parameter
CS low to ALE low
ALE low time
ALE high to RDY low
R/W setup time
R/W hold time
RDY low time
RDY high to CS high
CS to RDY active/tristate time
Address setup time
Address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
Parallel Bus Timing
Table 6
Minimum Nominal
0
-
70
-
-
-
50
-
50
-
100
-
-
-
-
-
50
-
50
-
50
-
50
-
50
-
50
-
Maximum
-
-
250
-
-
-
0
10
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Preliminary Data Sheet: TM060 Page 12 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice