STC3500 Datasheet, PDF (45/48 Pages) Connor-Winfield Corporation – INTEGRATED - STRATUM 3 TIMING SOURCE

Application Notes continued
Max_Pullin_Range register (0x06) - Set to the maximum allowed frequency offset for a reference.
Automatic reference selection is accompanied by per-reference selectable priorities. These are written to bits 2-0 of the
Ref(1-8)_Frq_Priority registers. The highest priority is 0 and the lowest is 7. For equal priorities, lower reference
numbers have higher priority. Active reference selection is then made according to priority and conditioned on
reference availability (registered in Ref_Available). See figure 7.
Each reference may also be marked as “revertive” or “non-revertive”, by writing bit 3 of the Ref(1-8)_Frq_Priority
registers to “1” for revertive or “0” for non-revertive.
When a reference becomes unavailable, the device automatically picks the available reference of next lower priority.
When a reference returns, it will be switched to only if it is of higher priority and the current active reference is marked
“Revertive”. Return to a previously failed reference is delayed by the value in the Ref_Rev_Delay register. Write a
value from 0 to 255 minutes to the Ref_Rev_Delay register for the desired delay. (See figure 7 in the Reference Input
Selection, Frequencies, and Mode Selection section).
If operating in a master/slave configuration, be sure to write the Ref_Mask and the Ref(1-8)_Frq_Priority registers to
the same values for both devices. Read the operational mode (lower 4 bits) from the master’s Op_Mode register, and
write them to the lower 4 bits of the slave’s Op_Mode (0x05) register. This needs to be repeated whenever there is a
reference switch on the master. To facilitate this, an interrupt (bit 4 of the Intr_Event register) is provided to indicate a
reference change. (Alternatively, the application may choose to poll the master’s Op_Mode register to detect reference
switches.)
Select the desired Hold Over history policy, “Continue” or “Rebuild”, by writing to the History_Policy register, (0x25).
The application may further save, restore, or flush the Hold Over history using the History_Cmd register (2x26), as
described in the Hold Over History Accumulation and Maintenance section.
The remainder of the registers provide access to device internals, such as synchronization state, reference activity and
quality, and operational customizations. Their use is at the discretion of the application. Some typical uses are
described below (see also the Register Descriptions and Operation section):
Phase_Offset (0x0e) - May be used to compensate for master/slave Sync_8K or Sync_Clk to Xref path-length or
clock distribution paths, as desired. Requires analytic/experimental technique to determine appropriate values. See
also Master/Slave Operation sections.
Calibration (0x0f) - This register can be used to compensate for a known OCXO/TCXO frequency offset. Write to a
value representing the difference between the oscillator’s measured frequency and the nominal frequency.
DPLL_Status (0x11) - This register provides active reference, lock, and Hold Over history status.
Interrupts - Five interrupts are provided for application monitoring and control of synchronization. They are individually
maskeable by the Intr_Enable register (0x13), and readable in the Intr_Event (0x12) register. Pin INTR is pulled low
when a non-masked interrupt occurs.
Ref_Qualified (0x0a) - May be read to determine if a reference is active and within the pull-in range.
Ref_Available (0x0c) - May be read to determine if a reference is qualified and not masked.
Ref(1-8)_Frq_Offset (0x13 -0x1a) - May be read to determine the frequency offset, in 0.2 ppm resolution, between
each reference and the local calibrated oscillator.
Ctl_Mode (0x04) - The state of the BITS_Sel and HM_Ref pins may be read from bits 2 and 3.
While the same information is available via register access, the LOS, LOL, and Hold_Avail status indication outputs
are also functional and may be used at the discretion of the application.
Ref(1-8)_Frq_Offset (0x13 -0x1a) - May be read to determine the frequency offset, in 0.2 ppm resolution, between
each reference and the local calibrated oscillator.
Ctl_Mode (0x04) - The state of the BITS_Sel and HM_Ref pins may be read from bits 2 and 3.
Holdover_Time (2x27) - The time, from 0 to 255 hours, since the Hold Over state was entered, may be read.
Preliminary Data Sheet: TM060 Page 45 of 48 Rev: P06 Date: 11/22/04
© Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice