DB929B Datasheet, PDF (46/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 46 of 50
MX929B PRELIMINARY INFORMATION
6.1.3.1 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence. (Tx output level is
proportional to V_DD).
4. Measured at the TXOUT pin with the modem in the Tx idle mode.
5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence,
TXIMP = 0 or 1. The optimum level and DC offset values are proportional to V_DD.
6. Timing for an external input to the XTAL/Clock pin.
7. WR , RD , CS , A0 and A1 pins.
8. D0 - D7 pins.
9. IRQ pin.
6.1.4 Timing
PC Parallel Interface Timings (ref. Figure 28)
t_{ACSL Address valid to CS low time}
t_AH
Address hold time
t_CSH
CS hold time
t_CSHI
CS high time
t_{CSRWL CS to WR or RD low time}
t_DHR
t_DHW
Read data hold time
Write data hold time
t_DSW
Write data setup time
t_{RHCSL RD high to CS low time (write)}
t_{RACL Read access time from CS low}
t_{RARL Read access time from RD low}
t_RL
RD low time
t_RX
RD high to D0-D7 3-state time
t_{WHCSL WR high to CS low time (read)}
t_WL
WR low time
Notes
1
2
2
Min.
0
0
0
6.0
0
0
0
90.0
0
200
0
200
Typ.
Max.
175
145
50
Units
ns
ns
ns
clock cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.1.4.1 Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to V_SS on D0 - D7 pins.
©2001 MX-COM, INC.
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.