DB929B Datasheet, PDF (37/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 37 of 50
MX929B PRELIMINARY INFORMATION
START
Ensure that the Control Register
has been loaded with suitable
CKDIV, FSTOL, LEVRES and PLLBW values
Ensure that the Mode Register IRQEN,
PSAVE, RXEYE, TX/RX, and SSIEN bits are '0',
and the INVSYM bit is set appropriately
Write a RESET task to the Command Register
Read the Status Register
Wait until the received carrier has been present
for at least 8 symbol times
Set µC variable 'STATE' to 0
Set the Mode Register IRQEN bit to '1'
Enable µC's MX929B Rx Interrupt Service Routine
Yes
BFREE bit = 1 ?
No
Write a SFP task to the Command Register
with the AQSC and AQLEV bits set to '1'
Note: during this time the µC may
perform other functions, as the
µC variable 'STATE' is updated
by the interrupt service routine
Yes
'STATE' < 4 ?
No
Disable µC's MX929B Rx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
END
with error
No
'STATE' = 4 ?
Yes
END
Figure 21: Receive Frame Example Flowchart, Main Program
Notes
1. The RESET command in Figure 21 and the practice of disabling the MX929B’s IRQ output when not
needed are not essential but can eliminate problems during debugging and if errors occur in operation.
2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command
Register.
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