DB929B Datasheet, PDF (36/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 36 of 50
MX929B PRELIMINARY INFORMATION
5.2 Receive Frame Example
The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences, Station
ID Block, and one each Header, Intermediate and Last blocks are shown below;
1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW
values, and that the IRQEN bit of the Mode Register is '1', the TX / RX , RXEYE, PSAVE, and SSIEN bits
are '0', and the INVSYM bit is set appropriately.
2. Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3).
3. Read the Status Register to ensure that the BFREE bit is '1'.
4. Write a byte containing a SFP task and with the AQSC and AQLEV bits set to '1' to the Command
Register.
5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the CRCERR and DIBOVF bits should be '0'.
6. Read 3 Station ID bytes from the Data Block Buffer.
7. Write a RHB task to the Command Register.
8. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the DIBOVF bit '0'.
9. Check that the CRCERR bit of the Status Register is ‘0’ and read 10 Header Block bytes from the Data
Block Buffer.
10. Write a RILB task to the Command Register.
11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the DIBOVF bit '0'.
12. Read 12 Intermediate Block bytes from the Data Block Buffer.
13. Write a RILB task to the Command Register.
14. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be ‘1’ and
the DIBOVF bit ‘0’.
15. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from the Data
Buffer.
Note:
1. The value of the latest ‘S’ symbol received will be contained in the SVAL bits each time the Status
Register is read. If desired, the Mode Register SSIEN bit may be set to ‘1’, which will cause a PC interrupt
after every ‘S’ symbol received, in which case the PC will have to distinguish between interrupts caused by
the BFREE bit going to ’1’ and those caused by SRDY bit being set to ‘1’.
2. Figure 21 and Figure 22 illustrate the host PC routines needed to receive a single Frame consisting of
Symbol and Frame Sync patterns, a Station ID Block, a Header Block, any number of Intermediate blocks
and one Last block. It is assumed that the Rx Interrupt Service Routine Figure 22 is called every time the
MX929B’s IRQ output goes low.
©2001 MX-COM, INC.
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.