DB929B Datasheet, PDF (27/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 27 of 50
MX929B PRELIMINARY INFORMATION
4.5.4.4 Mode Register B4: RXEYE - Show Rx Eye
This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the
modem for a special test mode, in which the input of the Tx output buffer is connected to the Rx Symbol/Clock
extraction circuit at a point which carries the equalized receive signal. This may be monitored with an
oscilloscope (at the TXOUT pin itself), to assess the quality of the complete radio channel including the Tx and
Rx modem filters, the Tx modulator and the Rx IF filters, and FM demodulator.
This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered
signal (before Rx equalization) is not very recognizable so it is generally not useful.
The resulting eye diagram (for reasonably random data) should ideally be as shown Figure 14, with 4 distinct
and equally spaced level crossing points.
Figure 14: Ideal 'RXEYE' Signal
4.5.4.5 Mode Register B3: PSAVE - Powersave
When this bit is a ‘1’, the modem will be in a ‘powersave’ mode in which the internal filters, the Rx Symbol and
Clock extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to V_BIAS
through a high value internal resistance. The Xtal clock oscillator, Rx input amplifier and the PC interface logic
will continue to operate.
Setting the PSAVE bit to ‘0’ restores power to all of the chip circuitry.
Note: The internal filters, and therefore the TXOUT pin in transmit mode, will take approximately 20 symbol-
times to settle after the PSAVE bit has gone from ‘1’ to ‘0’.
4.5.4.6 Mode Register B2: SSIEN - 'S' Symbol IRQ Enable
In receive mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a new
'S' symbol has been received. (The SRDY bit of the Status Register will also be set to '1' at the same time,
and the SVAL bits updated to reflect the received 'S' symbol.)
In transmit mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a 'S'
symbol has been transmitted. (The SRDY bit of the Status Register will also be set to '1' at the same time.)
4.5.4.7 Mode Register B1, B0: SSYM - 'S' Symbol To Be Transmitted
In transmit mode, these two bits define the next 'S' symbol to be transmitted. These bits have no effect in
receive mode.
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