DB929B Datasheet, PDF (40/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 40 of 50
MX929B PRELIMINARY INFORMATION
5.3.4 Automatic Acquisition Functions
Setting the AQSC and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level
Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude,
and DC offset as quickly as possible before switching to accurate - but slower - measurement modes. These
acquisition sequences act very quickly if triggered at the start of a received Symbol Sync pattern (as shown in
Figure 23), but will still function correctly, although more slowly, if started any time during a normal Frame as
when the receiver is switched onto a channel where the transmitter is operating continuously.
The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits
being put into 'Clamp' Mode for one symbol time to quickly set the voltages on the DOC pins to approximately
correct levels. The level measurement circuits are then automatically set to 'Lossy Peak Detect' mode for 15
symbol times, then 'Slow Peak Detect' until a received Frame Sync pattern is recognized, after which the
automatic sequence ends and the level measurement circuit mode reverts to the mode set by the LEVRES
bits of the Control Register (normally 'Level Track').
The peak detectors used in both 'Slow' and 'Lossy Peak Detect' modes include additional low pass filtering of
the received signal. This greatly reduces the effect of pattern noise on the reference voltages held on the
external DOC capacitors but means that pairs of '+3' (and '-3') symbols need to be received to establish the
correct levels. Two pairs of '+3' and two pairs of '-3' symbols received after the start of an AQLEV sequence
are sufficient to correctly set the levels on the DOC capacitors.
The automatic AQSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 16
symbol times (this mode is not one of those which can be selected by the Control Register PLLBW bits) then
changes to 'Wide' bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control
Register PLLBW bits.
5.4 AC Coupling
For a practical circuit, ac coupling between the modem's transmit output to the frequency modulator and
between the receiver's frequency discriminator and the receive input of the modem may be desired. There
are, however, two issues which deserve consideration:
1. AC coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph
illustrates the typical bit error rates at 4800 symbols/sec (9600bps) without FEC for reasonably random data
with differing degrees of AC coupling:
1.E-01
1.E-02
1.E-03
Tx & Rx DC coupled
Tx 5Hz, RxDC
Tx 5Hz, Rx5Hz
Tx 5Hz, Rx10Hz
1.E-04
4
5
6
7
8
9
10
11
12
13
14
S/N dB (Noise in 20 to 9600Hz band)
Figure 24: Effect of AC Coupling on BER (without FEC)
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