DB929B Datasheet, PDF (19/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
Page 19 of 50
MX929B PRELIMINARY INFORMATION
RXIN Signal
IRQ Output (IRQEN = '1')
IRQ Bit of Status Register
BFREE Bit of Status Register
Task from µC to Command
Register
Data from Block Buffer to µC
for Task 1
for Task 2
Task 1
Task 2
Task 1 data
Figure 10: Receive Task Overlapping
Detailed timings for the various tasks are provide in Figure 11 and Figure 12.
MX929B Modem Tasks:
B2 B1 B0
Receive Mode
0 0 0 NULL
0 0 1 SFP
Search for Frame Preamble
0 1 0 RHB
Read Header Block
0 1 1 RILB
Read Intermediate or Last Block
1 0 0 SFS
Search for Frame Sync
1 0 1 R4S
Read 4 symbols
1 1 0 RSID Read Station ID
1 1 1 RESET Cancel any current action
NULL
T24S
THB
TIB
TLB
T4S
TSID
RESET
Transmit Mode
Transmit 24 symbols
Transmit Header Block
Transmit Intermediate Block
Transmit Last Block
Transmit 4 symbols
Transmit Station ID
Cancel any current action
4.5.2.7 NULL: No effect
This is provided so an AQSC or AQLEV command can be initiated without loading a new task.
4.5.2.8 SFP: Search for Frame Preamble
This task causes the modem to search the received signal for a valid 24-symbol Frame Preamble, consisting
of a 24-symbol Frame Sync sequence followed by Station ID Block which has a correct CRC0 checksum.
The task continues until a valid Frame Preamble has been found.
The search consists of four stages:
First the modem will attempt to match the incoming symbols against the Frame Synchronization pattern
to within the tolerance defined by the FSTOL bits of the Control Register.
Once a match has been found, the modem will read in the following 'S' symbol, place it in the SVAL bits
of the Status Register then set the SRDY bit to '1'. (The IRQ bit of the Status Register will also be set to
'1' at this time if the SSIEN bit of the Mode Register is '1').
The modem will then read the next 22 symbols as station ID data. They will be decoded and the CRC0
checked. If this is incorrect, the modem will resume the search, looking for a fresh Frame Sync pattern.
If the received CRC0 is correct, the following 'S' symbol will be read into the SVAL bits of the Status
Register and the SRDY, BFREE, and IRQ bits set to '1', the CRCERR bit cleared to '0', and the three
decoded Station ID bytes placed into the Data Block Buffer.
Upon detecting that the BFREE bit of the Status Register has gone to '1', the µC should read the three Station
ID bytes from the Data Block Buffer and then write the next task to the modem's Command Register.
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