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DB929B Datasheet, PDF (23/51 Pages) CML Microcircuits – Full Data Packet Framing
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4-Level FSK Modem Data Pump
Page 23 of 50
MX929B PRELIMINARY INFORMATION
Data to Data Block Buffer
Task to Command Register
IBEMPTY Bit
BFREE Bit
Symbols to RRC Filter
Modem Tx Output
1
2
3
1
2
3
t4
t4
t4
t2
t3
t1
from Task 1
t2
t3
t2
t3
from Task 2
from Task 3
Figure 11: Transmit Task Timing Diagram
Modem Rx Input
Symbols to De-Interleave
Circuit
Data from Data Block Buffer
Task to Command Register
BFREE Bit
for Task 1
t5
t6 1
for Task 2
for Task 3
t5
t5
1
2
3
t6
2
t6
3
t7
t7
t7
Figure 12: Receive Task Timing Diagram
4.5.2.22 RRC Filter Delay
The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the
input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times
through to the RRC filter in both transmit and receive modes, as illustrated below:
Delay from Tx Input
symbol to TXOUT
response.
Tx Symbol to RRC Filter
Delay from Rx Input
(from FM discriminator)
to interpreted data in
internal buffer.
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
RX Symbol to De-Interleave Buffer
Symbol-times
Figure 13: RRC Low Pass Filter Delay
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