DB929B Datasheet, PDF (10/51 Pages) CML Microcircuits – Full Data Packet Framing

4-Level FSK Modem Data Pump
4. General Description
Page 10 of 50
MX929B PRELIMINARY INFORMATION
4.1 Description of Blocks
4.1.1 Data Bus Buffers
Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host µC's data
bus lines.
4.1.2 Address and R/W Decode
This block controls the transfer of data bytes between the µC and the modem's internal registers according to
the state of the Write and Read Enable inputs ( WR and RD ), the Chip Select input ( CS ), and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel µC interface, which can
be memory-mapped, as shown in Figure 3.
D0:7
A0:1
A2:7
µC
IRQ
WR
RD
Data Bus
Address Bus
V_DD
IRQ pull up
resistor
Address Decode
Circuit
D0:7
A0:1
CS
MODEM
IRQ
WR
RD
Figure 3: Typical Modem 2C connections
4.1.3 Status and Data Quality Registers
Two 8-bit registers which the µC can read to determine the status of the modem and received data quality.
4.1.4 Command, Mode, and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
4.1.5 Data Buffer
A 12-byte buffer used to hold, receive or transmit data to or from the µC.
4.1.6 CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which may be included in the transmitted data blocks so the receive modem can detect transmission
errors.
4.1.7 FEC Generator/Checker
In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the
conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols
to binary data, using the FEC information to correct a large proportion of transmission errors.
4.1.8 Interleave/De-Interleave Buffer
This circuit interleaves data symbols within a block before transmission and de-interleaves the received data
so that the FEC system is best able to handle short noise bursts or fades.
4.1.9 Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization
pattern that is transmitted to mark the start of every frame.
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