CMX972 Datasheet, PDF (39/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
8.1.3.4 AC Parameters – Integer N PLL and VCO
For the following conditions unless otherwise specified:
V_CC = V_CCSYNTH = V_DD = 3.3V; V_RFGND = V_SS = 0V. RXLO Level = -10dBm and Tamb = +25ºC.
Notes Min.
Typ.
Max.
Phase Locked Loop
Reference Input
Frequency
Level
Divide Ratios (R Counter)
Synthesiser
Comparison Frequency (f_comparison)
Input Frequency Range
Input Level
Divide Ratios (M Counter)
Charge Pump Current
1Hz Normalised Phase Noise Floor
Negative Resistance VCO
Supply Current (Enabled)
Frequency Range
Phase Noise at 10kHz Offset
Phase Noise at 100kHz Offset
5
40
–
2
–
30
0.5
–
–
8191
1
–
500
40
–
1000
-20
–
-5
80
–
32767
–
2.5
–
43
–
-216
–
–
3
–
41
40
–
1000
42
–
-104
–
42
–
-118
–
RXLO Input
Input Level
Frequency Range
–
-10
–
40
–
1000
Unit
MHz
Vp-p
kHz
MHz
dBm
mA
dBc/Hz
mA
MHz
dBc/Hz
dBc/Hz
dBm
MHz
Notes:
40.
41.
42.
43.
Sinewave or clipped sinewave.
Operation will depend on the choice and layout of external resonant components.
With external components from section 4.4 (Table 4) forming a 180MHz VCO; negative
resistance bits set to minimum ($2F, b1-b0 = ‘11’); phase noise quoted at VCO operating
frequency but will normally be improved by the divider circuits in the demodulator LO path.
1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within
the PLL loop bandwidth by: Measured Phase Noise (in 1Hz) = PN1Hz + 20log₁₀(M) +
10log₁₀(f_comparison).
 2015 CML Microsystems Plc
39
D/972/2