CMX972 Datasheet, PDF (25/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
Rx Offset Register b7 – b0
I/Q DC offset correction, see section 5.1.2 for further details.
Bit _{b3 b2 b1 b0 I Channel}
b7 b6 b5 b4 Q Channel
1 1 1 1 -420mV
1 1 1 0 -360mV
1 1 0 1 -300mV
1 1 0 0 -240mV
1 0 1 1 -180mV
1 0 1 0 -120mV
1 0 0 1 -60mV
1 0 0 0 No correction
0 1 1 1 +420mV
0 1 1 0 +360mV
0 1 0 1 +300mV
0 1 0 0 +240mV
0 0 1 1 +180mV
0 0 1 0 +120mV
0 0 0 1 +60mV
0 0 0 0 No correction
6.5.2 Rx Offset Register - $EF: 8-bit read
This read-only register mirrors the value in register $1F; see section 6.5.1 for details of bit
functions.
6.6 PLL M Divider Register
6.6.1 PLL M Divider - $2C - $2A: 8-bit write
These registers set the M divider value for the PLL (Feedback divider). The PLL dividers are only
updated when $2C has been written, so this register should be written to last. Bits 7 and 5 also
control the PLL and charge-pump blocks and these control bits are active as soon as $2C is written.
(Note: To enable the PLL, b2 of the General Control Register ($1B) also needs to be set).
Bit: ⁷
6
5
E LD_Synth CP
$2C
43
00
$2B
21
0
7
6
5
4
3
2 10
0 M17 M16 M15 M14 M13 M12 M11 M10 M9 M8
$2A
7
6
5
4
3
2
1
0
M7
M6
M5
M4
M3
M2
M1
M0
M17:M0
Phase Locked Loop M divider value.
CP
$2C, b5 = ’1’ enables the charge pump, $2C b5 = ’0’ puts the charge pump into high-impedance
mode.
 2015 CML Microsystems Plc
25
D/972/2