CMX972 Datasheet, PDF (26/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
LD_Synth
Only write ‘0’ to b6 of $2C (when read, this shows the PLL lock status, see section 6.6.2).
E
$2C, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL – in this mode an external local oscillator
may be supplied to the CMX972, see also section 5.3.2 and Table 14. (Note: To enable the PLL b2
of the General Control Register ($1B) also needs to be set).
$2C b4-b2
Reserved, set to ‘0’.
6.6.2 PLL M Divider - $DC - $DA: 8-bit read
These registers read the respective values in registers $2C, $2B and $2A ($DC reads back $2C
and $DB reads back $2B etc.); see section 6.6.1 for details of bit functions.
N.B. $DC b6 indicates the Synthesiser lock detect status.
6.7 PLL R Divider Register
6.7.1 PLL R Divider - $2E - $2D: 8-bit write
These registers set the R divider value for the PLL (Reference divider). The PLL dividers are only
updated when $2E has been written, so this register should be written to last.
$2E
$2D
Bit: ^{7 6 5}
4
3
2
1076543210
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
R15:R0
Phase Locked Loop R divider value.
6.7.2 PLL R Divider - $DE - $DD: 8-bit read
These registers read the respective values in registers $2E and $2D ($DE reads back $2E and
$DD reads back $2D); see section 6.7.1 for details of bit functions.
6.8 VCO Control Register
6.8.1 VCO Control Register - $2F: 8-bit write
This register optimises the operation of the VCO. Note the VCO is enabled when b3 = ‘1’ in the
General Control register ($1B), as detailed in section 6.2.
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
IMD5
6
IMD4
5
IMD3
4
IMD2
3
IMD1
2
IMD0
1
VCONR2
0
VCONR1
 2015 CML Microsystems Plc
26
D/972/2