CMX972 Datasheet, PDF (24/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
Bit:
7
M1
6
5
4
3
M0
DIFAMPI DIFAMPQ FREQ3
2
FREQ2
1
FREQ1
CMX972
0
FREQ0
Rx Mode Register b7 – b6
Bit _b7
0
0
1
1
b6
0 I and Q channels enabled
1 Only I channel enabled
0 Only Q channel enabled
1 Reserved do not use
Rx Mode Register b5 - b4
With b4, b5 = ‘0’ both differential amplifiers are enabled/disabled by the DIFAMP bit in the General
Control Register (section 6.2.1). With b4 = ‘1’ the Q channel differential amplifier control by the
DIFAMP bit will be inverted. With b5 = ‘1’ the I channel differential amplifier control by the DIFAMP
bit will be inverted. This aids the applications where the amplifiers are associated with either the I
or Q channels.
Bit _{$1B, b5}
0
0
0
0
1
1
1
1
b5 b4
0 0 Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘OFF’
0 1 Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘ON’
1 0 Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘OFF’
1 1 Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘ON’
0 0 Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘ON’
0 1 Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘OFF’
1 0 Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘ON’
1 1 Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘OFF’
Rx Mode Register b3 – b0
These bits optimise the operation of the receiver quadrature demodulator mixers by adjusting the
LO signal. The bits adjust LO amplitude, which has an impact on mixer gain, but the adjustment
also has an effect on quadrature accuracy. See also section 5.1.1. Note that if $1C b6 is set to 0,
so that phase correction is not used, the setting of these FREQ bits has no effect.
A setting of ‘0000’ represents the optimum value for phase accuracy.
6.4.2 Rx Mode Register - $ED: 8-bit read
This read-only register mirrors the value in register $1D; see section 6.4.1 for details of bit
functions.
6.5 Rx Offset Register
6.5.1 Rx Offset Register - $1F: 8-bit write
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
QDC3
6
QDC2
5
QDC1
4
QDC0
3
IDC3
2
IDC2
1
IDC1
0
IDC0
 2015 CML Microsystems Plc
24
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