CMX972 Datasheet, PDF (36/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
8.1.3 Operating Characteristics
8.1.3.1 DC Parameters
For the following conditions unless otherwise specified:
V_CC = V_CCSYNTH = V_DD = 3.3V; V_RFGND = V_SS = 0V. RXLO Level = -10dBm and T_AMB = +25ºC.
DC Parameters
Total Current Consumption
Powersave Mode
Bias Only
Operating Currents
Rx Only
PLL and VCO
Additional Current with DIFFAMP=’1’
Notes
1
2
4
5
6
Min.
–
–
–
–
–
Typ.
7
1.7
15
9
0.85
Max.
70
2
20
11
1.5
Logic '1' Input Level
Logic '0' Input Level
Logic Input Leakage Current (Vin = 0 to V_DD)
Output Logic ‘1’ Level (l_OH = 0.6 mA)
Output Logic ‘0’ Level (l_OL = -1.0 mA)
Power Up Time
Voltage Reference
All Blocks Except Voltage Reference
70%
–
–
–
–
30%
-1.0
–
+1.0
80%
–
–
–
–
+0.4
7
–
7
–
–
0.5
–
10
Units
µA
mA
mA
mA
mA
V_DD
V_DD
µA
V_DD
V
ms
µs
Notes:
1.
2.
3.
4.
5.
6.
7.
Total current, V_DD, V_CC and V_CCSYNTH.
Clock input (REFIN pin) not active; powersave mode includes the case after general reset with
all analogue and digital supplies applied and also the case with V_DD applied but with V_CC and
V_CCSYNTH supplies disconnected (i.e. in this latter scenario power from V_DD will not exceed the
specified value, whatever the state of the registers), not including any current drawn from
device pins by external circuitry.
Void
Only Rx and Bias sections active.
Only Bias, PLL and VCO sections active.
DIFFAMP bit in General Control Register, see section 6.2.1, combined current for both
differential amplifiers
Time from the rising edge of the last serial clock input following CSN being asserted for a write
to the appropriate control register.
 2015 CML Microsystems Plc
36
D/972/2