CMX972 Datasheet, PDF (16/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
Condition
COR = ‘0’ $1D = 0x00
COR = ‘1’ $1D = 0x00
COR = ‘1’ $1D = 0x0F
Typical I/Q Phase Balance
87.95
90.06
90.49
Table 10 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 250MHz
Condition
COR = ‘0’ $1D = 0x00, +20°C
COR = ‘1’ $1D = 0x0F, -20°C
COR = ‘1’ $1D = 0x0F, +20°C
COR = ‘1’ $1D = 0x0F, +55°C
Typical I/Q Phase Balance
87.3
90.6
90.6
90.5
Table 11 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 300MHz with Temperature
5.1.2 DC Offset Correction
Digitally-controlled dc offset correction is provided which is capable of reducing the offset to 60mV or less
for errors of up to +/-420mV. This represents a reduction in dynamic range of about 0.3dB for a typical
ADC input signal range (2Vp-p) and is therefore negligible. The required correction must be measured
externally as such measurements are application specific. The correction is applied close to the start of the
I/Q baseband chain and therefore maximises dynamic range in the analogue sections.
The correction is applied in a differential manner so positive and negative corrections are possible, see
Figure 11. This allows the dc to be corrected to the nominal dc bias level. The voltage sources are scaled
in a binary fashion so multiple sources can be added to provide the desired correction. The same
arrangement applies independently on both I and Q channels.
+
Vdc3
+
+
Vdc2
Vdc1
Vdc4
+
Vdc5
+
Vdc6
+
Positive
Terminal
Negative
Terminal
Figure 11 Simplified Schematic DC Offset Correction Circuit
Source
Vdc1
Vdc2
Vdc3
Vdc4
Vdc5
Vdc6
Voltage Correction at Output for
Maximum Gain in Baseband Amplifiers
60mV
120mV
180mV
60mV
120mV
180mV
Correction Polarity
Positive terminal increase,
Negative terminal decrease
Positive terminal increase,
Negative terminal decrease
Positive terminal increase,
Negative terminal decrease
Negative terminal increase,
Positive terminal decrease
Negative terminal increase,
Positive terminal decrease
Negative terminal increase,
Positive terminal decrease
Table 12 DC Offset Correction Adjustments
 2015 CML Microsystems Plc
16
D/972/2